Patents

Subject matter of the patents is:

Design Verification of SoC, 2.5D IC and 3DIC (stacked dies).
Progressive reusable refinement of Verification environment / testbench from Algorithm to RTL level.
Simulating RTL with TLM2.0 ESL Models.

9,646,128: SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS

9,625,971: SYSTEM AND METHOD OF ADAPTIVE VOLTAGE FREQUENCY SCALING

9,612,277: SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICS

9,552,448: METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION

9,404,971: CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING

9,158,881: INTERPOSER DEFECT COVERAGE METRIC AND METHOD TO MAXIMIZE THE SAME

9,110,136: CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING

9,047,432: SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS

9,015,649: METHOD AND APPARATUS FOR ELECTRONIC SYSTEM (ESL) MODEL GENERATIONS

8,972,918: SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICS

8,966,419: SYSTEM AND METHOD FOR TESTING STACKED DIES

8,826,202: REDUCING DESIGN VERIFICATION TIME WHILE MAXIMIZING SYSTEM FUNCTIONAL COVERAGE

8,578,309: FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFICATION METHODOLOGY (UVM)

8,522,177: METHOD AND APPARATUS FOR ELECTRONIC SYSTEM (ESL) FUNCTION VERIFICATION AT TWO LEVELS

8,402,404: STACKED DIE INTERCONNECT VALIDATION

8,336,009: METHOD AND APPARATUS FOR ELECTRONIC SYSTEM (ESL) FUNCTION VERIFICATION AT TWO LEVELS

9,514,268: INTERPOSER DEFECT COVERAGE METRIC AND METHOD TO MAXIMIZE THE SAME