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On Line Training

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Course 1:

SystemVerilog Assertions & Functional Coverage

In-depth from-scratch Course offered on UDEMY


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Course 2:

SystemVerilog Functional Coverage course offered on UDEMY

HIGHEST RATED Course on Udemy

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Course 3:

Comprehensive Verilog with Doulos

Teaches application of Verilog for FPGA and ASIC designs. Development of combinational and sequential (state machine) RTL design and synthesis. Also covers File I/O and Testbench development. 5 days/6 hours sessions.

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Course 4:

Comprehensive/Advanced VHDL with Doulos

Prepares you for practical project readiness for FPGA designs. Covers development of combinational and sequential RTL development and synthesis. Also covers File I/O and Testbench development. Coprehensive VHDL – 4 days/6 hours sessions

Advanced VHDL – 4 days/4 hours sessions

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Course 5:

EXPERT VHDL for Design and Verification with Doulos

Expert VHDL for Design

Advanced development of RTL for FPGA/ASIC design/synthesis/implementation. Reusable designs. Introduction to OVL/PSL

Expert VHDL for Verification

Advanced transaction level testbench development. Scoreboard development. BFM development. Introduction to OSVVM and UVVM.

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