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Ashok Mehta

Ashok Mehta has worked in the ASIC/SoC design and verification field for over 30 years. He worked at DEC, DG, INTEL, AMCC and TSMC. webp to jpg 19
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The Best Education Place

  • Expert Verilog Users. Verilog for Design and Verification
  • Expertise in SystemVerilog Assertions and Functional Coverage Languages and Methodologies
    • SVA can be applied to both Verilog and VHDL
    • SVA deployment does not require knowledge of SystemVerilog OOP subset or UVM
  • Expert Trainers in SystemVerilog Assertions and Functional Coverage
  • Behavioral/Architectural modeling in Verilog
  • Methodologies:
    • Coverage Driven Verification (CDV)
    • Assertion Based Verification (ABV)
    • Coverage Methodology (Code, Functional, Sequential Logic)
    • Constrained Random Verification (CRV)
    • Behavioral (modular, reusable) Testbench Methodology in Verilo
students and teacher
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