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DefineView Consulting

DefineView Consulting provides SystemVerilog, Comprehensive Verilog and Expert VHDL training (on-site and on-line) to ASIC/SoC Design and Verification engineering community at large.

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On-line Training

SystemVerilog Assertions & Functional Coverage: In-depth, from-scratch, course offered on UDEMY

4.5/5

600 Reviews (4.7 Rating)

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On-site Training

Comprehensive SystemVerilog Assertions and Functional Coverage on-site Training

4.5/5

200 Reviews (5.0 Rating)

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On-line Training

Introduction to SystemVerilog Functional Coverage course offered on UDEMY

4.5/5

250 Reviews (4.5 Rating)

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About Us

US PATENTS BY ASHOK MEHTA

Ashok Mehta have been granted 21 US Patents to date.
Subject matter of the patents is;

  • Design Verification of SoC, 2.5D IC and 3DIC (stacked dies).
  • Progressive reusable refinement of Verification environment / testbench from Algorithm to RTL level.
  • Simulating RTL with TLM2.0 ESL Models.
Why Choose Us

Experience Since 1991

Ashok Mehta has worked in the ASIC/SoC design and verification field for over 30 years. He worked at DEC, DG, INTEL, AMCC and TSMC.

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Books

BOOKS BY ASHOK MEHTA

SystemVerilog Assertions and Functional Coverage provides an application oriented in-depth guide to language, methodology and applications of SystemVerilog Assertions and Functional Coverage Languages. Used by engineering community at large, it will serve as an excellent Reference Book.

SystemVerilogBook
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