DefineView Consulting provides ASIC/SoC Design Verification expert training (both on-site and on-line) to design and verification engineering community at large.
On-line Training
SystemVerilog Assertions & Functional Coverage: In-depth, from-scratch, course offered on UDEMY
CLICK HERE TO TAKE THE COURSE
On-site Training
Comprehensive SystemVerilog Assertions and Functional Coverage on-site Training
1-day training Agenda
2-days training Agenda
Introduction to SystemVerilog Functional Coverage course offered on UDEMY
“SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications” (Third Edition : Springer 2020).
“ASIC/SoC Functional Design Verification: Comprehensive guide to technologies and methodologies” (Springer: 2018)
“Introduction to SystemVerilog” – Springer 2021”
This book covers entire SystemVerilog language (except for PLI/DPI, Specify Block, Gate level)
Ashok holds 21 US Patents in the field of SoC design verification (CLICK HERE).
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